Embodiments of the present invention relate to a method for manufacturing an integrated sensor structure. Further embodiments of the present invention relate to an integrated sensor structure. Further embodiments of the present invention relate to a method for manufacturing a CMOS-integrated sensor structure and to a CMOS-integrated sensor structure.
It is know from literature [Ke Wang, Harvey A. Fishman, Hongjie Dai and James S. Harrist, “Neural Stimulation with a Carbon Nanotube Microelectrode Array” Nano Letters 2006 6 (9), 2043-2048] that depositing CNTs (Carbon Nano Tubes) as a functional layer onto electrode structures improves the charge transfer capacity and improves cell growth onto the electrodes.
When depositing CNTs directly onto the electrodes on a CMOS (Complementary Metal Oxide Semiconductor) substrate, the difficulty resulting is that “normal” CMOS substrates are damaged irreparably using conventional CVD (Chemical Vapor Deposition) methods, due to the comparably high depositing temperature for the functional layer (such as, for example, CNTs) of roughly 700° C. necessary. The influence of the additional temperature budget of depositing the functional layer generally causes non-tolerable parameter shifts of devices (such as, for example, transistors) and damages of, for example, the metallization (in particular in aluminum metallization, which is frequently used in CMOS technology, with a comparably low melting point) and contacts, for example caused by the “spiking effect” by the barrier layers failing (such as, for example, by the formation of cracks).
This gives rise to a wide spread view, which has also been published repeatedly [Wang, X; Zhang, Y; Haque, M. S.; Teo, K. B. K; Mann, M; Unalan, H. E.; Warburton, P. A.; Udrea, F; Milne, W. I.; “Deposition of Carbon Nanotubes on CMOS,” Nanotechnology, IEEE Transactions on, vol. PP, no. 99, pp. 1.0 doi: 10.1109/TNANO.2009.2038787], that it is not possible to apply functional or sensor layers, like CNTs, directly onto a CMOS structure using a high-temperature CVD method, after finishing the metallization of the CMOS substrate.
The prior art known thus states either using alternative depositing methods for CNTs, such as, for example, low-temperature “hot filament” deposition [Wang, X; Zhang, Y; Haque, M. S.; Teo, K. B. K; Mann, M; Unalan, H. E.; Warburton, P. A.; Udrea, F; Milne, W. I.; “Deposition of Carbon Nanotubes on CMOS,” Nanotechnology, IEEE Transactions on, vol. PP, no. 99, pp. 1.0 doi: 10.1109/TNANO.2009.2038787] or else special low-temperature CVD depositions [S. Hofmann, C. Ducati, J. Robertson and B. Kleinsorge, “Low-temperature growth of carbon nanotubes by plasma-enhanced chemical vapor deposition”, Appl. Phys. Lett. 83, 135 (2003), doi: 10.1063/1.1589187]. Additionally, “cold” depositing methods, such as, for example, dip coating a suspension onto a CMOS structure or dielectrophoresis for “cold” orientation of the CNTs between electrodes are resorted to [Sung Min Seo; Jun Ho Cheon; Seok Hyang Kim; Tae June Kang; Jung Woo Ko; In-Young Chung; Yong Hyup Kim; Young June Park; “Carbon Nanotube-Based CMOS Gas Sensor IC: Monolithic Integration of Pd Decorated Carbon Nanotube Network on a CMOS Chip and Ist Hydrogen Sensing, “Electron Devices, IEEE Transactions on, vol. 58, no. 10, pp 3604-3608, October 2011 doi: 10.1109/TED.2011.2164249]. A different approach uses special heating structures which are integrated into the CMOS element and which allow locally heating up the electrodes, without thereby damaging the surrounding CMOS transistors. An example of such a CMOS structure comprising an integrated micro heater is described, for example, in the publication by [Sumita Santra, Syed Z Ali, Prasanta K Guha, Guofang Zhong, John Robertson, James A Covington, William I Milne, Julian W Gardner and Florin Udrea, “Post-CMOS wafer level growth of carbon nanotubes for low-cost microsensors—a proof of concept”, 2010 Nanotechnology 21 485301 doi: 10.1088/0957-4484/21/48/485301].
The methods mentioned above suffer from the disadvantages of losses in quality of the layers or in the depositing speed achievable for the layers or comparably large apparatus expenditure for low-temperature deposition.